Rumoured AMD RDNA 5 specs point to impressive performance gains but one detail raises eyebrows

[Redaktion]

A new rumour outlines alleged specifications, performance targets and pricing for AMD's next-generation RDNA 5-based Radeon RX 10000 series. It makes some interesting claims, such as the use of LPDDR5X memory modules on lower-end models.

https://www.notebookcheck.net/Rumoured-AMD-RDNA-5-specs-point-to-impressive-performance-gains-but-one-detail-raises-eyebrows.1340196.0.html

[P. Le Gal]

9.5A per pin is setting a very high bar for the connector. The industry should seriously consider a new standard with more voltage instead.

[doesnt line up]

"One possible explanation for LPDDR5X VRAM is cost. "

The 256-bit, 256 GB/s, Strix Halo APU (4060 Laptop level of performance) uses LPDDR5X-8000, but problem is, LPDDR5X prices have quadrupled. Being 256-bit makes the Strix Halo APU quite expensive.
Per pin / bit bus memory lane, LPDDR5X is much slower than GDDR7 and so a much wider and hence bigger GPU chip is required.
RX 9060 XT has at 320 GB/s memory bandwidth already. A next-gen GPU, namely a 10060 XT, would have to be, say, (at least) 30% faster -> 320 GB/s * 1.3 = 416 GB/s. So the GPU chip would have to have a 416-bit memory bus width, or a multiple of 16-bit per LPDDR5X channel. 416-bit is actually divisible by 16-bit per channel (just a coincidence) = 26 channels. For comparison, a RTX 5090 has a 512-bit memory bus width.

And even if the 320 GB/s are correct, using LPDDR55X-8000 means still a 320-bit memory bus width chip. Such a chip is big and hence expensive. For comparison, a 9070 XT is a 256-bit chip.

(en.wikipedia.org/wiki/Radeon_RX_9000_series#Desktop)


"connector reliability is problematic to this day. "
Correct. From today even: notebookchat.com/index.php?topic=315411.0.