Apparently, AMD was considering implementing Intel's Foveros 3D technology at some point, but later decided to develop a better proprietary Micro Bump 3D packaging that is 1 micron thinner and quite a bit more efficient. This is only the beginning, as AMD plans to refine the interconnect pitch in the future, allowing for more complex 3D stacking applications.
https://www.notebookcheck.net/AMD-presents-more-details-on-Zen-3-3D-V-Cache-and-the-future-of-3D-stacking.556527.0.html
"decided to develop a better proprietary Micro Bump 3D packaging"
Didn't TSMC develop all of the packaging technologies that AMD is using?
"We will probably see the first application of the IP on IP technique with the RDNA2 GPU cores stacked on top of the Zen 4 cores."
Why would they stack two of the hottest parts of Raphael together? That seems more like a Zen 10 innovation when they go full 3D.
"19% in content creation applications"
That I did not know.
Quote from: Anonymousgg on August 25, 2021, 00:17:24
"decided to develop a better proprietary Micro Bump 3D packaging"
Didn't TSMC develop all of the packaging technologies that AMD is using?
That is correct.
"We will probably see the first application of the IP on IP technique with the RDNA2 GPU cores stacked on top of the Zen 4 cores."
NOTHING in that leak article suggests that Raphael will be IP on IP.
"Although only 1 micron thinner than Intel's Foveros 3D stacking that will be used to produce the Alder Lake processors..."
I don't believe Alder Lake uses Foveros 3D stacking. Xe-HPC uses foveros 3D stacking, but not at the 10u pitch.
I believe the Intel's 10u pitch is associated with foveros direct, which was described in Aug, 2020 as their hybrid bonding.
Could you present your source for the Alder Lake foveros claims?