Posted by: DanEE« on: May 25, 2020, 21:29:30 »
I suspect the only reason that Intel added "sub channels" and AMD added "virtual channels" support is to get boards to route without adding layers and cost. The floor planning of the die and ball assignments are designed in SOC's to make it easier to route for two separate channels with single channel devices or DIMMs. The trace length matching, specified in pico-seconds, for pairs, bits in a lane and between lanes is very tight. To have the buses cross would be a nightmare to route. I did many DDR and LPDDR designs over the years.
The Comet Lake U parts support LPDDR4x and not LPDDR4 and datasheet says 2 64bit wide channels. The LPDDR4x spec added a single channel option, where as all LPDDR4 parts were dual channel. It doesn't have the sub channels or their associated register definitions. It will one or two 64bit bus(es) in a LPDDR4x configuration.
LPDDR4/x can be added in parallel to form any width. The UM433IQ uses 4 32bit (2, 16bit channels) LPDDR4 to make 4 32bit channels. It really is a routing and cost issue.
It will be interesting to see what happens with LPDDR5.