With the first 2 nm chips planned for a 2025 release, TSMC could theoretically ready the 1.4 nm nodes by 2028. Samsung will most likely come up with a similar node around the same time, while Intel will try to get ahead of the game with the 20A and 18A nodes in 2025.
https://www.notebookcheck.net/TSMC-expected-to-announce-plans-for-its-1-4-nm-production-nodes-next-month.621042.0.html
TSMC and Samsung's 2nm (or 7nm for that matter) are not using transistors with a 2 nanometer gate width. Their "2nm" is just as indicative (or misleading) as intel's 20 angstrom
Quote from: Humanrich on May 21, 2022, 03:17:14
TSMC and Samsung's 2nm (or 7nm for that matter) are not using transistors with a 2 nanometer gate width. Their "2nm" is just as indicative (or misleading) as intel's 20 angstrom
Hopefully most people know that by now. What do we want, a disclaimer at the top of every article?
We still don't have any info on TSMC N2 peformance, power, and area improvements as far as I know. It would be nice to get that to see the effect of GAAFETs.
The article author needs to be aware of ASML and their delivery timelines on High NA before listing statements of "Apparently, Intel will be the first to use the higher numerical aperture lithography with the 20A and 18A nodes in 2025" when ASML won't be testing it's first completed High NA until next year, isn't delivering pre-production prototypes until 2024, and production models until 2025. This agrees with their investment notes from 2021 and recent news this past week. So Intel being in production with them for 20A and 18A is a stretch unless one is talking about very low volumes in Q3/Q4.
"ASML said it had five orders for pilot machines, which should be delivered in 2024, and "more than five" orders from five different customers for faster production models for delivery starting in 2025."
seekingalpha.com/article/4433147-asml-stock-next-gen-euv-tool-delayed-by-three-years
www.fudzilla.com/news/54884-asml-high-na-version-of-euv-prototype-ready