Detailed Strix Halo and Strix Point specifications surface courtesy of official leaked AMD document

[Redaktion]

Zen 5 and RDNA 3.5-based AMD Strix and Strix Halo APUs are on their way with the promise of massive performance gains. Now, a leaked official AMD document has apparently detailed specifications of Strix Point and Strix Halo products with the latter enjoying more than 3 times the Compute Units of the Radeon 780M.

https://www.notebookcheck.net/Detailed-Strix-Halo-and-Strix-Point-specifications-surface-courtesy-of-official-leaked-AMD-document.831274.0.html

[Mr Majestyk]

Should also point out that Halo will come with a 256 bit bus vs 128 bit for normal Strix Point. That will also help feed the iGPU as well as the LPDDR5 8000

[Cyrax]

Sh*t, power range from 45W to 65W for Strix Point with Zen 5c cores is too much! It looks like AMD is going to say goodbye to power efficiency...

Ohh AMD, I was hoping for you after Intels unimpressive efficiency gains 😔
I think, the last hope is from Qualcomm and its X Elite...

[NikoB]

Strix is garbage by igpu. Only Strix Halo with DP2.1/UHBR20 is of practical interest with the prospect of connecting 8k monitors in lossless data transfer mode.

Although, taking into account the fact that Zen5 will actually appear on sale no earlier than 2025, it turns out to the shame of the entire IT industry, they deliberately delayed the real mass introduction of DP2.0+/UHBR20 into hardware for 6 years! This is the craziest delay in IT history since the standard was published!

By the time Zen5 comes out, I'm sure all dgpu chips 2025 will also have DP2.0+/UHBR20, so igpu with slow RAM (even a pathetic 256-bit memory bus won't help if it's actually introduced) simply won't be needed by anyone , one of those owners whose goal is precisely the ability to connect an 8K monitor(s) with ideal text and graphics clarity (as on smartphones).

AMD/Intel were stupidly late with the integration of DP2.0+/UHBR20 into mainstream graphics by 3 years and the fault for this is entirely theirs - their x86 cores have been suffocating for many years from slow RAM, which simply could not withstand the transfer of lossless streams at the igpu level for 8k resolution. They needed to increase the bit capacity of the memory controller to 256 back in 2021.

And now we need not 256, but 512. Although the implementation of the 512-bit Apple controller turned out to be essentially a fake - the real efficiency is 4 times lower than the declared one.

All this is very sad - time is lost. And we are not eternal...