Willkommen im Forum! Hier können sie über alle unsere Artikel und allgemein über Notebook relevante Dinge disuktieren. Viel Spass!

Main Menu

Intel Alder Lake architecture overview: Heterogeneous ISA, dynamic Thread Director, shared 30 MB L3 cache, and more

Started by Redaktion, October 27, 2021, 18:00:23

Previous topic - Next topic


Intel's new 12th gen Alder Lake platform brings with several notable changes on the architecture side. Alder Lake processors use a heterogeneous ISA with a shared L3 cache and an intelligent Thread Director that helps the OS in proper scheduling of threads. The CPU brings support for DDR5-4800 RAM and PCIe Gen5, but the Z690 chipset supports only PCIe Gen4 and Gen3.


This is not a heterogeneous ISA. This is heterogeneous microarchitecture. Please make the correction. This heading is technically highly wrong. ISA means instruction set architecture. Microarchitecture is its implementation. Which are the heterogeneous cores here. One ISA can have many implementations.


"There is also support for up to 4x USB 3.2 Gen2x2, 10x USB 3.2 Gen2, 10x USB 3.2 Gen1, and 14 USB 2.0 ports, so connectivity shouldn't be an issue at all. Finally, there are eight lanes of SATA 6 Gb/s ports for storage expansion. "

Unfortunately, they wont implant it in the motherboards...

So dont hope to see a motherboard with  4x USB 3.2 Gen2x2

Jatin Bhateja

Title of this article is misleading, Alderlake is not an Heterogeneous ISA but it's a Heterogeneous Architecture. ISA is still homogeneous.

Quick Reply

Warning: this topic has not been posted in for at least 120 days.
Unless you're sure you want to reply, please consider starting a new topic.

Please leave this box empty:

Shortcuts: ALT+S post or ALT+P preview